 About RISC RISC stands for Reduced Instruction Set Computer. It is a technique for making faster computers that has been around for a while now but hasn't been widely used in desktop machines. The major philosophical difference between conventional or CISC (Complex Instruction Set Computer) computers and RISC is that instead of having a large set of slow, complicated instructions the computer can perform, RISC has a small set of fast instructions. The program used to write programs, the compiler, is responsible for assembling these small instructions into efficient units to perform the required task. Computers have a basic speed of operation measured in millions (or billions) of cycles per second or megahertz (MHz or GHz). The problem is that conventional computers take several cycles to perform one instruction. For example a Mac Plus takes about 8 to perform one, so an 8MHz Mac really only does 1 million instructions each second. RISC technology allows the computer to do one instruction every cycle (sometimes more) so a 110 MHz PowerMac can do about 100 million instructions each second. This is usually achieved by using several advanced techniques such as caching, pipelining and superscalar architectures. About Pipelining Pipelining is a technique used to increase the performance of computers. Basically, it involves breaking instructions into small parts and processing different parts of a sequence of instructions at the same time. For example when one instruction is being executed the next one could be having a required address calculated and the one after that could be being interpreted. About Superscalar Architecture Superscalar architectures increase the speed of computers by executing several instructions at the same time. For example the PowerPC 601 processor has 5 pipelines so it can theoretically execute 5 instructions simultaneously. The pipelines are specialised: there are two integer, two floating point and one branch prediction, so the real speed gain depends on the program. That is one reason why programs need to be re-written to take full advantage of the PowerPC. Note that the discussion above applies to quite old RISC chips, but the argument is the same today. Also note that some CISC architectures can also make use of these techniques, but they tend to become even more bloated and buggy as a result. Arm Systems on a Chip At the WWDC 2020 Apple announced that they would start moving some Mac models to the CPU architecture already used in devices like the iPhone and iPad, sometimes known as "Arm". This originally came from a company, Advanced RISC Machines, and before that (in the 1980s) Acorn RISC Machines. Apple build the actual processors (more technically, systems on a chip, or SoCs) and license the instruction set from Arm. As the name suggests, these processors use a RISC architecture, which offers many advantages in speed and power use over more conventional processors, like those made by Intel. Early tests show the new processors easily out-performing the old Intel ones. Apple might be able to use this as a point of difference (superiority) for future Macs over future PCs. It should also make running iOS apps on Macs much easier. RISC versus CISC For most tasks, RISC is a superior architecture. Unfortunately Apple was forced to move to CISC chips and used the major producer of most PCs processors: Intel. The first Intel-based Mac appeared in 2006. This was more a decision based on the realities of business at the time (Apple's partners for PowerPC chips: Motorola and IBM, were losing interest and not investing in the platform) so Intel was the logical choice. Those processors did the job OK, but as time went by (moving into 2020) Intel processors were compromised by delays, poor performance, and bugs. This is exactly what I would expect from a design with fundamental flaws being pushed beyond its real capabilities. Note that Intel got fairly good performance out of their processors, and Intel Macs (and PCs) were pretty good, but the future is clear: that architecture (and maybe Intel itself) is a dead end.
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RISC ARCHITECTURE